In January of this year--about two years after it shipped the first 90-nanometer Prescott--Intel began shipping 65-nm versions of its Pentium D Presler processor. Intel has now shipped more than 40 million 65-nm processors.
In the normal course of events, other major integrated device manufacturers--like Advanced Micro Devices, IBM and Texas Instruments--would have followed up on the release of a 65-nm Intel processor with releases of their own microprocessors at the same node. Shortly thereafter, the major fabless semiconductor vendors would have offered their 65-nm products, typically FPGAs from Altera (fabbed by Taiwan Semiconductor Manufacturing) or Xilinx (fabricated by United Microelectronics).
Oddly enough, however, there were few 65-nm products in volume production at the end of October, although there do appear to be a few new entrants on the horizon. Semiconductor Insights has early samples of both AMD's 65-nm processor and Xilinx's Virtex-5 (built on UMC's 65-nm process). AMD and Xilinx have announced that they will begin shipping 65-nm versions of their products in December. IBM, however, says that its new 65-nm flagship processor, the Power 6, won't be in volume production until the middle of 2007.
The challenges at 65 nm clearly ac- count for some of the slowdown. The lithographic challenges to patterning 65-nm features seem to have been met, however. Now the real challenge is how to improve performance by 30 percent without blowing the power budget.
Most manufacturers have slightly decreased the gate length (Intel has gone down to 40 nm in the Presler, from 65 nm in the Prescott) without decreasing the gate oxide thickness at all beyond the 90-nm technology value (typically on the order of 1.2 nm). Any further reduction in gate oxide thickness causes massive gate leakage currents. In the absence of viable high-k gate dielectrics, the only possible strategy left is to increase the amount of nitridation of the gate oxide--which, judging from published results, appears to offer only marginal benefits.
Stresses on strain
To eke out the requisite 30 percent performance benefit, then, the burden falls to materials changes, notably channel strain engineering. Although strain engineering worked at the 90-nm node, it is a far more complicated solution than straightforward scaling of the gate length and gate oxide. For one thing, PMOS and NMOS devices need different and opposite strain values to improve their performance (compressive for PMOS and tensile for NMOS). In addition, the common strain solutions used at the 90-nm node were nitride stress liner layers of selective silicon germanium source drains. Both solutions induce local rather than global strain. An unwanted result is subtle, layout-dependent effects.
The design challenges at the 65-nm node are also significant. Increasingly restrictive design rules are required to ensure adequate yields. Process variations are magnified by the increasingly smaller features. With a gate oxide thickness of six or seven atoms, even atomic-level variation in the gate oxide thickness leads to significant performance variation. Similar effects present themselves in the interconnect layers. The chemical-mechanical planarization technique used to pattern copper interconnect can create layout-dependent thickness variation in the metal lines, leading ultimately to unacceptable timing variation.
IBM appears to have solved the performance problem, however, judging by the specifications on its Power 6 processor. The company claims that when it debuts in 2007, the processor will have double the clock frequency, at 5 GHz, and half the instruction execution time at 3 nanoseconds per instruction, compared with the 90-nm Power 5 within the same power envelope.
The IBM process includes a silicon-on-insulator substrate, a 35-nm physical gate length, a 1.05-nm gate oxide, low-k dielectric at eight of the metal levels and a 0.65-micron2 SRAM cell.
The question remains, though: Why is the rest of the industry lagging Intel? Intel certainly gains an enormous advantage from its business model, which is predicated on selling a high-volume, pretty much single product into the continually up- grading, short-development-cycle PC market. In contrast, IBM's Power 6 is aimed at the high-end server and mainframe markets, which have much longer development cycles, typically requiring co- development of new software and operating systems.
For the foundries, the explanation may be simple economics. Traditionally, they have developed processes aimed more at achieving higher density than higher performance. Few of their customers can justify the huge development costs of a 65-nm product, particularly when 90-nm products are doing fine. Further, few actually need a 65-nm process, particularly when performance is not as critical. Thus the risks and costs of designing into a 65-nm process outweigh any benefits of smaller die size.
The exceptions to this are real estate-hungry FPGA devices. High-density FPGAs typically have the largest die size of any high-volume integrated circuit. Not surprisingly then, the Xilinx Virtex-5, fabbed at UMC, has just been released. With a die size of 145 mm, it is easy to see why a 65-nm process was required. The Virtex-5 has between 30k and 330k logic cells, depending on the specific model, operating at a 550-MHz clock speed. SI's analysis on the Virtex-5 has begun, and it will be interesting to see what process choices have been made in the UMC 65-nm process. It should mark the first use of strained silicon by a foundry.
Until now, AMD has been the odd man out, but it will catch up in December when the company ships its product. And certainly its lack of a 65-nm product does not appear to have hurt sales in the short term. The company has continued to chip away at Intel's share of the X86 market. According to research firm Mercury Research, AMD increased its share of the X86 server processor market to 25.9 percent in the second quarter. Intel holds 72.9 percent of the overall market for X86 processors, while AMD has 21.6 percent. Clearly, good circuit design and device architecture can make up for deficits in process technology.
In sum, the process technology horse race has changed significantly at the 65-nm node, with one competitor clearly leading by several lengths, followed by a much more spread-out field. The true winners will be the companies that have made the right choices relative to their own business models.
Edward Keyes(edward@ semiconductor.com) is chief technology officer of Semiconductor Insights (Kanata, Ontario).
