Intel Corp.'s highly anticipated 90-nanometer StrataFlash cellular memory (M18) family is now available, and it does not disappoint. The device evaluated by Semiconductor Insights, with a part number of 28F512M18, is the most advanced NOR device on the market, thanks to its effective die size and its performance advantages. The 512-Mbit NOR flash operates on a 1.8-volt power supply, has a burst frequency of 108 MHz and a die size of 43.8 mm². The 28F512M18 uses Intel's multilevel-cell (MLC) technology to store 2 bits in one memory cell, effectively doubling the density of the flash.
The M18 is targeted at the mobile embedded-flash marketplace. The 512-Mbit density positions the device to hit the sweet spot of embedded-memory requirements for next-generation cell phones. From Semiconductor Insights' analysis, the M18 is more advanced than any other NOR flash on the market today and positions Intel ahead of its nearest NOR rival, Spansion LLC. Technologically, Intel was significantly ahead of Spansion's mobile NOR offering, but Spansion was able to shrink the gap with a 110-nm offering earlier this year. The M18 device reinforces Intel's technological leadership, with Spansion's 90-nm wireless offering not expected until mid-2006.
The M18 is manufactured using the ninth generation of the Etox process, which can trace its roots to the first flash development at Intel in 1983. The first chips rolled out in the mid-1980s were 64-kbit devices that were manufactured on 1.5-micron technology with a cell size of 36 square microns. The M18 represents nearly a four-order increase in memory size and more than a 470 times reduction in cell size in those two decades.
See image: Die comparison of Intel's StrataFlash 130-nm (left) and 90-nm devices.
The M18 is built on the same Etox IX 90-nm process as Intel's single-bit W18 device. Scaling aside, there are many similarities in features with the 130-nm generation. The basic floating-gate structure of this and previous generations appears to be scalable to at least 65 nm. In fact, the cell area factor (F) for the Etox IX cell is well ahead of the International Technology Roadmap for Semiconductors' prediction of 11 to 14 for 90-nm NOR flash. Intel has obviously taken care to build a strong memory array support mechanism in the peripheral circuits.
Copper metallurgy and low-k dielectrics (fluorinated silicate glass, or FSG) provide the backbone of the control circuitry of the M18. Intel may claim another first, since no other commodity memory device in production uses copper interconnects. The move to copper gives Intel designers more flexibility to route longer signal lines. But the main advantage is the speed performance specification that the M18 and future revisions can hit that vendors waiting to move to copper will not.
Intel process engineers have a long history of turning out powerful transistors. That manufacturing muscle is leveraged heavily on the M18. The Etox IX process employs an aggressively scaled transistor that is 50 percent smaller than the 130-nm flash device. This gives a big boost to M18 designers who need to minimize the real estate for peripheral logic and maximize silicon utilization for the memory array. Bigger drive currents gave the designers one more tool for faster clock speeds and longer signal routing.
The M18 process is a great package. From high-speed copper lines to aggressively scaled logic transistors and efficient flash cell design, Intel has set the bar for NOR flash with the M18.
Do die size, shape matter?
The M18 is visually similar to previous versions of Intel StrataFlash products examined by Semiconductor Insights. However, a few subtle differences have a major impact on the device's performance and versatility. One of the most significant differences is the aspect ratio of the die-the ratio of the width and length. Previous StrataFlash devices were often very tall relative to their width. But in the M18, width is comparable to the device's length, a small difference but one that has larger implications from a design and application viewpoint.
To manufacture a wider die, Intel needed to be able to extend the length of its bit lines, the lines that access the memory cell, so that they can reach across the die. A longer bit line has more capacitance and resistance, two factors that can degrade the speed and accuracy of the sensing scheme. Memory manufacturers can use different bit line architectures such as a local/global bit line arrangement, but this negatively impacts die efficiency.
Intel uses the local/global bit line architecture, but has extended the lengths of its global bit lines. The copper metallization and FSG dielectric used for the M18 have enabled this architecture. That's because the copper bit lines have a lower resistance, while the FSG dielectric reduces the capacitance.
The new aspect ratio was chosen to allow Intel to stack the M18 with itself and other devices. For package-stacking reliability, it is important for the dice to be similarly sized. The ability to stack packages is important in mobile memories because of the premium on pc-board space.
Die efficiency
The M18 die also has a good die-efficiency rating-the ratio of the area occupied by the memory cells vs. the total die area. The simple die efficiency is 46 percent. But after accounting for MLC technology, die efficiency rises to 92 percent. This is superior to Spansion's die efficiency of 35/70 percent on 110 nm.
The die-efficiency rating is good because of the design decisions Intel made with respect to the array architecture and to the aggressive reduction in the size of the peripheral transistors.
Not only is the die efficiency good, but the die size also yields a megabit/mm¹ rating of 11.6. That rating, more than twice as large as its nearest competitor, provides a more-universal benchmark for the effectiveness of a device's die size. A rating of 11.6 Mbits/mm² is comparable to single-level-cell NAND flash devices from vendors like Micron, Samsung and Hynix, devices that could compete in the embedded realm with StrataFlash.
The M18 also has a redesigned memory cell sensing scheme, streamlined circuit design and a more-comprehensive redundancy scheme. The revision of the memory cell sensing scheme is the most significant of these modifications, since it represents a change in a core circuit element that was not touched in previous StrataFlash devices.
Traditionally, Intel has used a current-reference sensing scheme, which compared the current from a reference memory cell to the current from the read memory cell to determine the stored value. Instead of using a reference cell, the M18 uses a stepped reference voltage generator, or a reference voltage, to read the contents of the memory cell.
The reference-voltage sensing scheme improves the sensing margin and, subsequently, the reliability of the sensing operation. The new sensing scheme is more immune to temperature fluctuations and is not affected by variations in reference current. Intel has said the new sensing architecture will allow the company to better scale its flash technology into the 65- and 45-nm process nodes. Therefore, the redesign of this component at the 130- to 90-nm transition will help Intel transition its flash technology to more-advanced geometries.
Analysis of the M18 has also revealed a more-streamlined circuit design. The data path analysis has highlighted this streamlined approach, which reduces circuit area and allows a faster operating speed.
Further, the M18 has considerable redundancy that takes up a large amount of die space. Redundancy is a hot topic in the memory industry, because redundant circuits occupy die area, increasing the cost per die. But redundant circuits can increase yield, because they increase the number of good dice. Unlike buyers of NAND flash, NOR flash customers do not expect bad sectors, so redundancy is important.
Intel has chosen to increase yield at the expense of die cost, most likely due to the effectiveness of the die.
The 90-nm StrataFlash is targeted at the mobile market, which requires NOR flash for code execution and memory storage. According to analysis from Semiconductor Insights' Handset Design Win subscription service, the sweet spot for NOR flash in the bulk of today's handsets is 128 Mbits to 256 Mbits. We anticipate that this number will move upward as cell phone integration and complexity increase.
It is unclear whether the mobile-phone market will move toward NAND flash. If it does, the M18 will present a reasonable alternative to NAND flash solutions. The device features increased reliability, reduced power consumption and a megabit/mm² rating that is competitive with 1-Gbit/2-Gbit single-level-cell NAND flash. So the 512-Mbit device will be able to meet these requirements and fend off the efforts of NAND flash vendors to get design wins in low- to midend phones.
The M18 also has a deep power-down mode and a 108-MHz burst speed. The power-down mode is very critical to handset manufacturers looking to extend battery life. The burst speed also shows a significant improvement over current versions of the StrataFlash, which have burst speeds of 54 MHz.
The M18 reinforces Intel's technical leadership in the NOR flash market space and creates a gap between itself and its nearest direct competitor, Spansion. The Intel device has a significant advantage over its main rival in many of the critical cost and performance categories. Spansion has announced that its 90-nm wireless device is due out in the second quarter of 2006 and has announced production in 90 nm for its Ornand and GL MirrorBit devices. If Spansion is able to meet this schedule, the product will have gained significant ground on StrataFlash.
Intel's focus will now shift to 65 nm and, depending on the release date of Spansion 90-nm wireless devices, could very well extend its technology lead. Then the question will be how well the M18 technology scales to the 65-nm node.
Geoff MacGillivray, (geoffrey@semiconductor.com), memory analyst at Semiconductor Insights (Kanata, Ontario)
