The recent launch of Intel Corp.'s Presler architecture coincided almost perfectly with the release of the 2005 edition of the International Technology Roadmap for Semiconductors. The new road map philosophy is quite evident in the Presler (officially, the Pentium D 900 series). The ITRS committees want to avoid the term "technology node," which focuses so much on lithography, and instead use unambiguous references to specific feature pitches, in hopes that
manufacturers will define their usage in each case--for example, the metal-1 pitch of their specific product. The balance is between "lithography enablers" and "technology enablers," as Intel refers to them in its road maps.
This new era of material-limited device scaling is embodied in Intel's transition from 90 to 65 nanometers, where critical transistor features were scaled little or not at all. Intel continues to use 193-nm dry lithography at 65 nm, with no new materials technology. The 65-nm technology enablers are low-k interconnect dielectrics, strained silicon and nickel silicide, just as they were for 90 nm. However, Intel has improved the strain enhancement of the second generation.
Fortunately for Intel, the juggernaut that pushed processor clock frequencies ever higher was driven by an outstanding semiconductor processing team that let the company shift its advanced manufacturing to begin to optimize for power. Intel is respinning the message as much as the technology. Instead of upping clock speeds, Intel presentations now point out that very small transistor gates exhibit lower capacitance that keeps leakage and power to a minimum.
Basic dimensions
The 65-nm Pentium D Processor 930 uses a 35-nm physical gate length, 1.2-nm physical gate dielectric, enhanced channel strain, nickel silicide, eight layers of copper interconnect and low-k intermetal dielectric for dense, high-performance logic. Lithography is at 193 nm, with alternating phase shift mask technology on critical layers to provide aggressive design rules. A six-transistor SRAM cell size of 0.57 micron2 was reported for Intel's 70-Mbyte SRAM test chip. We have confirmed a number of these features, but some clarification is necessary.
The 930D package is a 775-land flip-chip land grid array that replaces die solder bumps to reduce the lead content for green product guidelines. First metal is single-damascene copper, followed by seven via-first dual-damascene copper levels with TaN/Ta bilayer barrier. Carbon-doped oxide (CDO) is used as a low-k dielectric at several lower interconnect levels. By using CDO and adding carbon to the nitride etch stop layers, Intel claims to have reduced interconnect capacitance by 5 percent.
For decades, Intel has shrunk gate lengths to increase drive current and operating frequency. The company is now taking advantage of tiny gates by using this smaller footprint for gate leakage and capacitance to concentrate on power savings. Presler transistors are designed with various gate lengths. The smallest are slightly less than 40 nm. The minimum pitch of contacted polysilicon is 0.22 µm.
Intel has changed the basic SRAM design to achieve higher bit-cell densities. The new layout takes advantage of the large metal interconnect stack, replacing polysilicon word lines with third-level copper. It is similar to the design first introduced by Texas Instruments Inc. a few years ago. The 6T, 2.2-Mbyte Level 2 cache SRAM cell measures 0.48 x 1.31 µm, for a cell size of 0.63 µm2. The 120-kbyte L1 cache uses the same 0.63-µm2 design. Although some analysts jumped to the conclusion that the Presler cell would be the same size as the 65-nm SRAM test chip that Intel announced, it is actually slightly larger, since the MPU design is scaled up to improve production yield. The 0.63-µm2 cell size is midway between the published measurements for the L2 design and the larger, faster L1 design at 0.68 µm2 described in Intel's announcements of the low-power P1265 process.
