Overview:
This three part web seminar will address the latest Calibre solutions for advanced verification:
- Part 1: eqDRC – Solutions for Advanced Layout Checking
- Part 2: gridDRC – Solutions for Restrictive Design Rules
- Part 3: PERC – Solutions for Advanced ERC, ESD, and Multi Power Domain Checking
What You Will Learn:
- How eqDRC enables simple specification of difficult checks, providing greater accuracy and design area reduction
- How eqDRC can improve yield and reliability issues by accurately modeling complex failure mechanisms
- New methods for implementing Restrictive Design Rule checks How to resolve the debug challenges associated with advanced equation based and restrictive design rules
- How Calibre PERC combines the schematic level topology recognition with geometric checks to enable customized ERC checks including ESD and multiple power domains
Who Should View:
- Design Verification Engineers and Managers
- CAD Engineers and Managers
- Design Rule Definers and Writers
- Anyone working in the physical verification area of design
Presenter:
David Abercrombie
David Abercrombie is the Advanced Physical Verification Methodology Program Manager at Mentor Graphics. For the last four years he has been driving the roadmap for developing EDA tools to solve the growing issues in design to process interactions (DFM) that are creating ever increasing yield problems in advanced semiconductor manufacturing.
Previously, David has 15 years of experience driving yield enhancement programs in Semiconductor manufacturing at LSI Logic, Motorola, Harris and General Electric. He has also led software development teams in delivering yield enhancement and data mining solutions to semiconductor manufacturing.
He received his BSEE from Clemson University in 1987 and his MSEE from North Carolina State University in 1988.
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