Overview:
Power, noise, and reliability is one of the critical design challenges for system engineers today, Shrinking geometry, increasing functionality, higher input-output (I/O) signaling speed, low-power / low-leakage design techniques, and advanced packaging technologies such as system-in-package (SiP) exacerbate management of power, noise, and reliability challenges. What's required is a chip-package co-design methodology that enables co-analysis and co-optimization across chip, package, and system with package-aware IC and IC-aware package / system solutions.
In this webinar, Apache Design Solutions will explore proven chip-package co-design methodology followed by application examples of Cisco's networking system designs. The presentation will discuss co-design methodology based on a chip power model (CPM) that accurately represents the switching noise of the die's power delivery network. The presentation will demonstrate how CPM can be used during early stage prototyping to optimize package/board designs resulting in the most cost effective products. The presentation will include other applications on ways to control system timing variation due to power supply noise and jitter and discuss the types of system failure that are detected, such as system-level DDR jitter issue, and how the solution allows designers to analyze and fix problems prior to tape-out.
What will be covered:
In this educational webinar, Apache and Cisco will detail the methodology and technology used for integrated Chip-Package co-design. The webinar will include design examples from Cisco to demonstrate application and results. Specifically, the webinar will discuss:
Chip power integrity with impact of package and board
Early system prototyping with accurate chip power model
Methodology for chip-aware package analysis and optimization
Who should attend:
Physical designers working on designs especially at 90nm or below
Signal integrity engineers
Package and system power deliver network design engineers
Design methodology and design architects
Presenter:
Bhavana Thudi, Manager of Strategic Initiatives, Apache Design Solutions
Bhavana Thudi is currently a Manager of Strategic Initiatives at Apache Design Solutions working on power and noise analysis initiatives. Ms. Thudi received her Master of Science degree in Electrical Engineering from University of Michigan-Ann Arbor where she worked on advanced timing analysis algorithms for switching window computation in the presence of delay noise. She holds a Bachelor of Engineering degree in Electrical Engineering from Birla Institute of Technology & Science, Pilani, India.
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