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On-Demand Webinar
Selecting the Optimal Embedded Memory IP Architecture
Abstract:

As demands for increasing performance and features are being placed upon semiconductor designers, the amount of on-chip memory continues to grow. Selecting the most optimal embedded memory IP for the application is becoming progressively more important to avoid performance "bottlenecks", reduce system power consumption and cost. Higher resolution displays, advanced 3D graphics, streaming video and higher quality audio are some typical applications that require large amounts of data to be processed, and can benefit from high density, high-performance and low power embedded memory IP.

In this webinar:

  • Learn how to select the optimal embedded memory architecture for memory intensive SoC designs.
  • Hear about the benefits of high-density memory and the implications on manufacturing and wafer costs.
  • Discover the differences and benefits between 1T and 6T SRAMs.
  • See how the DesignWare coolSRAM-1TTM and coolSRAMTM IP enables designers to address low power, high performance and high density goals.

    Estimated length: 1 hour

    Who should attend: SoC design engineers, managers and architects

    Moderator:

    Clive "Max" Maxfield has now spent over a quarter of a century in the electronic, computing, and EDA arenas. In 1980, after obtaining his BSc in Control Engineering (an interesting mixture of math, electronics, mechanics, and hydraulics and fluids), Max joined a design team at International Computers Limited (ICL) creating CPUs for mainframe computers. In addition to designing ASICs and circuit boards, Max has written numerous test programs for functional and in-circuit testers. In the area of digital logic simulation, Max has created models of everything from ASIC cell libraries to microprocessors. Due to his digital expertise, Max was once appointed analog marketing manager at a large EDA company (the world is a funny old place sometimes).

    In the early 1990s, Max thought it would be fun to see a book he'd written on the shelves in his local book store, so he penned his first tome Bebop to the Boolean Boogie (An Unconventional Guide to Electronics). Since that time, Max has authored and co-authored a number of books, including EDA: Where Electronics Begins, The Design Warrior's Guide to FPGAs, and How Computers Do Math (Featuring the Virtual DIY Calculator).

    Presenters:

    Esin Terzioglu, Ph.D.
    Chief Technology Officer and Co-Founder, Novelics

    Novelics co-founder Esin Terzioglu serves as chief technology officer for the company, overseeing technical strategy, hiring and organization. Dr. Terzioglu is responsible for managing the engineering projects and innovations for the company's embedded memory technologies.Prior to co-founding Novelics, Dr. Terzioglu held key technical positions at Broadcom Corporation from 1999 to 2005, progressing from staff scientist to principal scientist. He led the development of four generations of embedded SRAM memory technology, contributing to industry-leading achievements in memory area efficiency, power and speed. Dr. Terzioglu has published 11 technical papers in the areas of fabrication processes, device physics and superconducting electronics, and holds more than 50 patents, mainly in circuit design and semiconductor memory technologies. Dr. Terzioglu received his bachelor's of science in electrical engineering from the University of Rochester, his master's of science and his Ph.D. in electrical engineering from Stanford University with a minor in computer science.

    Christophe Berteau-Pavy
    Product Marketing Manager, Synopsys

    Christophe Berteau-Pavy joined Synopsys in 1998. In his current position, Christophe is responsible for embedded memory IP product line as well as managing distribution of foundation IP from foundry partners. He has handled multiple product lines in the Synopsys DesignWare IP portfolio over his 10 years with the company. Prior to joining Synopsys Christophe held R&D positions at LSI Logic and Thomson and worked on system level verification and ASIC design methodology. Christophe holds a BSEE from the EFREI engineering school in Paris.


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    Email: webinar@techonline.com

  • Synopsys, Inc. (Nasdaq:SNPS), a world leader in software and IP for semiconductor design and manufacturing. The company delivers technology-leading system and semiconductor design and verification platforms, IC manufacturing and yield optimization solutions, semiconductor intellectual property and design services to the global electronics market. These solutions enable the development and production of complex integrated circuits and electronic systems. Through its comprehensive solutions, Synopsys addresses the key challenges designers and manufacturers face today, including power management, accelerated time to yield and system-to-silicon verification. Synopsys is headquartered in Mountain View, California, and has more than 60 offices located throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com. View the Synopsys Privacy Policy.
     
    Original Broadcast Date
    May 01, 2008
    Status
    Available On-Demand
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