Mentor Graphics

One of the most notable consequences of the semiconductor industry moving to deeper nanoscale technology nodes is the significant growth in both the number and densities of embedded memories. Designs have migrated from containing a handful of memories to containing hundreds and in some cases over a thousand memories of all types. This explosion in embedded memories is driving the need for rethinking the manufacturing test strategy for these designs. In particular, embedded memories now represent in most cases a die's largest contributor to yield loss due to the very large area and density of these regular circuits. A successful memory strategy must now incorporate some form of repair methodology in order to achieve profitable yield levels. Formulating a repair methodology often requires combining IP from memory providers, automation from DFT providers, and data from foundries. This often represents a significant challenge as not only are there several combinations and choices to consider, but more importantly, there is generally very little information on how to best make these choices. This paper attempts to address this challenge by explaining the memory repair process along with all of its components and choices as well as by providing repair related information on popular memory IP vendors and foundries.