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This paper explores the techniques for signal integrity prevention and repair in the Olympus-SoC place and route system. Signal integrity (SI) is a growing problem as higher interconnect density, increasing wire and via resistance, larger variations in resistance, lower threshold voltages, and faster clock speeds conspire to reduce the noise immunity of digital CMOS circuits. Reaching SI closure requires concurrent analysis of timing, power and SI interactions simultaneously across all the different modes and corners, a process referred to as multi-corner, multi-mode (MCMM) optimization.