Mentor Graphics

Reducing power consumption has become a key design challenge at 45/32 nm technology nodes. For many designs, optimizing for power is as important as timing, due to the need to reduce package cost and extend battery life. However, the complexities of designing low-power chips can negatively impact performance and time to market. Designers are being forced to juggle macro-level functional complexity issues (multiple operational modes), and micro-level process and manufacturing issues (multiple design corners) that could have conflicting power, timing, signal integrity (SI), manufacturability, and area closure requirements. In this paper, we will explore techniques currently used in low power IC design, describe the primary challenges of low-power design, and discuss how the Olympus-SoC place and route system implements the optimal low-power solution through all steps of the physical design flow.