The majority of ADCs manufactured today are used in sampled data systems, where the input waveform is sampled with a high frequency clock and the resulting data stream is processed in a DSP system of some sort. Since the DSP also requires a clock oscillator it is common practice to use a single oscillator to generate both the processor clock and the sampling clock. This oscillator is frequently constructed on the digital part of the system and uses the digital power supply—this results in substantial phase modulation of the oscillator by digital noise. In addition the actual oscillator design is rarely optimized for internal phase noise. This module analyses the degradation of sampled data system SNR (signal to noise ratio) by clock oscillator phase noise and proposes more suitable techniques for clock oscillator design, layout and siting.