Actel
This document illustrates a step-by-step process for synthesizing, placing, and routing an HDL generated design that is targeted to a QuickLogic device using the Precision RTL Synthesis tool and the QuickLogic FPGA design environment software tool, QuickWorks SpDE.
Note: By clicking on the above link, this paper will be emailed to your TechOnLine log-in address by Mentor Graphics.
|
