John Swanson
Synopsys

To meet increasing time-to-market pressures, designers have been using more intellectual property (IP) to reduce the amount of new code that needs to be created for the design. Additionally, on-chip bus standards such as the AMBA methodology have been widely adopted, providing designers with a standard that allows them to integrate multiple complex IP blocks as a subsystem into a system-on-chip (SoC) design.

This article describes how using a knowledge-based IP design and verification flow with coreAssembler™ can greatly reduce the time needed to assemble, configure, verify, and implement a configurable AMBA subsystem with IP architected and packaged for reuse.