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ESC SV-500- Embedded Applications of Multithreading
Radhika Thekkath Dir, Business and Strategic Planning, MIPS Technologies
Module
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DESCRIPTION
Multithreaded architectures exploit explicit parallelism to extract more throughput from a single processor. Embedded SoC designs can exploit this for greater area-efficiency, or for better real-time responsiveness. While the programming models of multithreaded and multiprocessor systems are fundamentally similar, the optimal choice of multithreaded CPUs, multiple independent cores or multiple multithreaded cores is application-dependent. This class explores the trade-offs and discusses considerations in selecting the best solution, covering symmetric and distributed-memory multiprocessing as well as different approaches to multithreading.

PREREQUISITES
Course Price $19.95
A basic understanding of multiprocessing principles and computer system architecture is assumed.

ESTIMATED TIME
84 minutes

AUTHOR

Radhika Thekkath Dir, Business and Strategic Planning, MIPS Technologies
Radhika was previously director of architecture for MIPS Technologies, where she worked on various architectural innovations, including the MIPS-3D® extension, the PDtrace™ architecture and the MIPS® DSP extension. She joined the company in 1998 after a stint at Equator Technology, and prior to that worked for two years for RISC pioneer John Hennessy at Stanford University. Radhika holds a Ph.D. in computer science from the University of Washington (Seattle, WA), and holds 28 U.S. patents.
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Embedded Systems Conference (ESC)