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ESC SV-446- High Speed Signal Processing with FPGAs and CPUs
David Hawkins Senior Scientist, Caltech
Module
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DESCRIPTION
The class details the design of a high-performance data processing system containing multiple FPGAs, embedded CPUs, and general-purpose CPUs. FPGAs handle high-speed, parallel, custom bit-width signal-processing tasks, embedded CPUs handle integer, floating-point, averaging (high dynamic range), and FFT operations, and general-purpose CPUs handle data management and server-like operations. FPGA signal-processing is presented, including: NCOs, FIR filtering, correlation, digital modulation, and custom bit-width, and optimized signal-processing operations - the build-what-you-need advantage of FPGAs relative to their CPU and DSP counterparts.

PREREQUISITES
Course Price $19.95
Basic familiarity with signal-processing and FPGA technology assumed.

ESTIMATED TIME
86 minutes

AUTHOR

David Hawkins Senior Scientist, Caltech
Dr. David Hawkins is currently involved with the design and development of high-speed digital correlator systems for Caltech, University of Chicago, and the CARMA (Caltech, Berkeley, University of Illinois, and University of Maryland)radio observatories. Prior to his work at Caltech, David was involved with the development of Synthetic Aperture Sonar(SAS), the underwater counterpart of Synthetic Aperture Radar(SAR).
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Embedded Systems Conference (ESC)