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Optimize Your Micro-server SoC Architecture for Performance and Power

Original Air Date: Oct 10, 2013 | Duration: 60 minutes Webinar
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Overview:
Broadband video, social networking, cloud-based services – these types of residential, business, and mobile networking applications are driving a tremendous increase in traffic and placing significant demands on the data center to improve system efficiency and reduce space, cost, and power.

One way the industry is responding to this challenge is with the development of low power, server-on-chip architectures: the micro-server SoC. The goal of the micro-server SoC is to significantly reduce power through integration of server motherboard functions for common tasks such as web servers, search engines, on-line transactions, and video-on-demand. For SoC architects, challenges include determining the right trade-offs between low power and high performance operation, the need for cache coherency, optimizing interconnects that are scalable to many cores, and implementing the right combination of dedicated HW accelerators to meet the needs of these dynamic application workloads.

In this session we will address the architecture design challenges associated with HW-SW partitioning and cache coherent interconnect optimization for the micro-server SoC and how early architecture simulation with Synopsys Platform Architect enables design teams to achieve the right system performance, power, and cost.

Who should attend:
System Designers, Product Architects, SoC Architects, and Project Managers

What Attendees will learn:
A Micro-server SoC case study example will be used to illustrate how architects can:

  • Create an application performance model of typical server workload, by specifying the timing characteristics (processing cycles, activation interval ) and memory access requirements of application-specific communication and compute tasks
  • Create a combined power/performance model of the micro-server SoC architecture that contains multicore processing elements, caches, cache-coherent interconnect, and memories, including annotation for power consumption
  • Map the application model to SoC architecture model in order to measure, analyze, and explore: 
    • End-to-end application latency and throughput for different server workloads
    • The utilization and power consumption of SoC components (cores, interconnect)
    • The impact of cache parameters and cache coherency on system performance
    • How architectural options further optimize application workload mapping
    • And how to optimize the use of CPU cores

Presenters:


Patrick Sheridan, Senior Staff Product Marketing Manager, Synopsys



Tim Kogel, Solution Architect, Synopsys

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