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Webinar Series: Managing Power, Noise and Reliability across Chip-Package-System

Original Air Date: Oct 15, 2013 | Duration: 60 minutes Webinar
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September 17, 2013 – October 15, 2013

This series provides experience sharing and ‘how-to’ methodologies by ANSYS-Apache customers and technical experts for meeting the ever-growing power noise challenges for chip, package and system designs. The series includes presentations by STMicroelectronics on best practices for power optimization of ARM core sub-systems and by Nvidia on proven methodologies for ESD verification and failure diagnosis. In addition, ANSYS-Apache power experts will discuss technologies and solutions for RTL power budgeting, IP and SoC power integrity and sign-off, chip-package-system convergence and reliability validation for advanced process designs.

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