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Debug and Bring-Up Automation for the HAPS-70 Series FPGA-Based Prototyping System

Original Air Date: Sep 26, 2013 | Duration: 60 minutes Webinar
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Overview:
FPGA-based prototypes offer tremendous value for system-on-chip validation and hardware/software integration by delivering high capacity, fast clock performance, and real-world I/O connectivity. The combination of performance and high-fidelity makes software integration and development tasks feasible months before test silicon is available. But when something goes wrong, debugging a complex prototype can be challenge. This webcast explores debug and bring-up automation features unique to the next-generation FPGA-based prototyping system, the Synopsys HAPS-70 Series. The HAPS-70 integrates troubleshooting and design visibility features to help reduce the effort to bring SoC/ASIC prototypes up quickly.

What will you learn during this webcast:

  • How to quickly import simulator debug views into a HAPS-70 series FPGA-based prototype
  • How to avoid prototype assembly and distribution problems with HAPS-70 series system self-checks
  • How HAPS-70 eases block-level validation of IP with high-capacity debug storage
Who should attend this webcast:
  • ASIC/SoC prototyping and emulation specialists
  • ASIC/SoC hardware designers
  • ASIC/SoC verification specialists
Presenter:

Ajay Jagtiani, Synopsys Inc.

Ajay Jagtiani is a staff CAE here at Synopsys focused on Debug and FPGA Prototyping tools. He holds an MBA in financial analysis from the University of San Francisco, an MSEE from Stevens Institute of Technology and a BSEE from Bombay University. Most of his career Ajay has worked in field of FPGA in marketing and application roles at various companies such as Altera, Lattice Semiconductor, and Synplicity.



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