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Design methodology and solutions for state-of-the-art ESD protection

Original Air Date: Jun 27, 2013 | Duration: 45 minutes Webinar
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Overview:
Damage by electrostatic discharge is a permanent threat to valuable electronics, requiring robust protection solutions. In this webinar is presented:

  • Methodology for a systematic ESD protection design
  • Key performance parameters of ESD protection devices
  • Latest developments to meet the challenge of protecting high data-rate ICs
Duration: 45 Minutes

Prerequisites: Basics of semiconductor devices and circuitry.

Attendees will learn:
  • A methodology enabling systematic ESD design
  • Understand ESD devices key performance parameters
  • Learn to know latest developments in ESD protection devices
Who should attend:
  • Application Engineers
  • Design Engineers
  • Test Engineers
  • Product Managers
Presenter:
Kim Lee, Applications Engineer, Infineon, North America
Kim Lee has worked in the electronics industry professionally for over 26 years. He currently serves as Applications Engineer supporting Infineon's ESD related issues for North America and manages the ESD Test Lab in Milpitas, CA.

He graduated Northeastern University and attended University of California at Berkeley. For over 20 years he has been involved with ESD, from component to system level as well as many years with lightning surge, power fault and other safety hazards in the datacom and telecom applications.

Kim has a diverse background from IC/Hybrid Design, IC Product & Test Engineering, Applications Engineering supporting mixed signal products from ADC/DACs, DFE/AFEs, and interface products for datacom/telecom applications to discrete components and amplifiers.

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