Achieving Predictable and Highly Reliable 10G Backplane Designs
This webinar explores the challenges of implementing 10 Gbps backplane systems, which can include PCB traces of 30" or longer with multiple connectors. Highly reliable 10G backplane systems require bit error rates (BER) better than 10-12, which goes beyond the base specification of most standards. To understand the challenges and options, the webinar will walk through a system case study and present representative channels. It will explore the architectural and circuit techniques required to meet stringent requirements, including the trade-offs associated with PLL implementation and receiver equalization.
Estimated Length: 60 Minutes
Who should attend: Systems designers, SOC designers, backplane designers
What attendees will learn:
- Challenges of backplane system design
- Techniques for compensating channel impairments
- Benefits and tradeoffs of channel equalization
- Design considerations for low bit error rates (BER)
David Rennie, Senior Analog Design Engineer for Mixed-Signal Interface IP, Synopsys
David Rennie is a Senior Analog Design Engineer for Synopsys' Mixed-Signal IP, developing next-generation high-speed PCIe® and Ethernet SerDes technologies. David has authored and co-authored fifteen IEEE conference and journal papers and holds five granted and three pending patents. He has presented at several industry and IEEE conferences, and is an active member in the IEEE.