Chip Aware System Design

Overview:
This webinar will focus on co-simulation methodologies for time and frequency domain simulations. A theoretical review of package/PCB modeling will be presented with a revisit of ABCD networks as related to S and Z parameters. An overview of chip-level extraction will be given with a discussion on how to include chip models in a system-level simulation. The goal is to provide engineers with methods that successfully design power delivery networks with the chip to ensure system metrics are met in context of the system as a whole, rather than individual parts.

What attendees will learn:

• Power Delivery Network (PDN) design requirements
• ABCD Matrix theory
• SYZ Matrix theory
• Chip-level Extraction
• Effect of Chip inclusion on time and frequency domain system simulations

Presenters:
Dr. Steven Gary Pytel Jr., Lead Signal Integrity Product Manager, Ansoft Product Line, ANSYS
Dr. Steven Gary Pytel Jr. is currently employed with ANSYS, INC., as the Lead Signal Integrity Product Manager for the Ansoft product line. He received a Doctor of Philosophy specializing in Signal Integrity from the University of South Carolina. Steve previously worked at Intel Corporation as a Senior Signal Integrity and Hardware Design Engineer where he helped design Blade, Telecom, and Enterprise servers. His current research interests include high speed serial signaling, statistical analysis of digital circuits, and hybrid electromagnetic field solvers. He has over 30 publications along with several invited papers and presentations. He has written an invited chapter on signal integrity simulation for Maxwell's Equations: The Foundations of Signal Integrity authored by Paul G. Huray.

Matt Elmore, Principal Applications Engineer, Apache, Design Inc
Matt Elmore is a Principal Applications Engineer at Apache, Design Inc, a wholly-owned ANSYS subsidiary. Mr. Elmore joined Apache in October 2005. Prior to joining Apache, he worked for several years at Zarlink Semiconductor where he supported their complete front-to-back design flow. Mr. Elmore's current focus includes creating and formalizing chip-package-system analysis and modeling flows in the Sentinel product suite. He holds a BSEE and MSEE from the University of California, San Diego.