Ridgetop Group discusses Solder Joint Built-in Self-Test™

Overview:
In this webinar you will be presented with an overview of Ridgetop's Solder Joint Built-in Self-Test™ (SJ BIST). Solder joint connections in ball grid array (BGA) packages are especially subject to cumulative fatigue damage. Prior to development of Ridgetop's SJ BIST product, there were no known methods for detecting intermittencies and high-resistance defects in functioning solder joint networks related to BGA packages. The cumulative damage eventually caused the solder joint to crack, usually at the package or printed circuit board (PCB) boundary.

SJ BIST is designed to detect static and dynamic occurrences of interconnect resistance increases and then alert the system regarding the condition of interconnect and related solder joints. Maintenance is thus facilitated, either through replacement or by switching to a redundant system prior to catastrophic failure. In addition to solder joint health monitoring, SJ BIST serves a wide range of applications where interconnect integrity and reliability are of concern.

Learning objectives:

• Interconnection reliability aspects
• SJ BIST's capabilities, operation and applications

Presenter:
Hans Manhaeve, Ph.D., CEO, Ridgetop Europe
Hans Manhaeve is CEO of Ridgetop Europe. Ridgetop Europe is based in Bruges, Belgium and is the new name for Q-Star Test of which he was founder, president and CEO. Ridgetop Europe provides unique, cost-effective, highly reliable solutions for IC and electronic circuits and systems testing to global semiconductor companies, addressing both the existing Q-Star Test business and supporting other Ridgetop products and services. Dr. Manhaeve has significant experience in the semiconductor industry and has worked with a wide variety of electronic product manufacturers within IC, automotive, medical control, telecommunications, networking devices, sensors & transducers and consumer from well-known Fortune 100 to smaller companies.

Dr. Manhaeve is very experienced with FPGA, IC and ASIC design, including: IC test, test strategy development and improvement, design for test methodologies (SCAN, BIST, Boundary Scan, and related technologies) and application, fault models, fault grading, test vector generation, ATPG, digital / mixed-signal circuit testing, memory testing, (supply) current based test, (supply) current based design for test, IDDX monitor design and development for on-chip and off-chip applications, IDDQ, IDDT, IDDX, BICS, IDDX application strategies, reliability screens, quality screening, 0ppm support.  Dr. Manhaeve earned his Ph.D. in Electronic Engineering from the University of Hull in February 1997, and his Electrical Engineering Degree (MSc) in Electronics from KIHWV (Technical University of Oostende) in 1987.