Embedded Memory Test and Repair Solution: Keeping Up with Changing Design Applications and Shrinking Process Technologies
With technologies shrinking and design complexity increasing, it is critical that embedded memory test and repair solutions keep up with the advances in order to consistently provide superior test quality and yield optimization. The embedded test approaches developed for designs done a few years ago are not sufficient for today's designs, which are bigger, faster, hierarchical and much more sensitive to area, timing and power. Similarly, the embedded test solutions developed for 90-nm technology nodes will not deliver the same level of test quality, diagnosis accuracy and repair efficiency for 28-nm technology nodes, as memory defects and failure mechanisms change as process technologies shrink. We will present the key points of interest for implementing embedded memory test, repair and diagnostics solution in today's designs.
What you will learn:
- The technical trends and challenges associated with embedded test, repair and diagnostics in today's designs.
- The trade-offs and design impact of various solutions.
- How Synopsys' DesignWare® STAR Memory System® can meet your embedded test, repair and diagnostics needs.
Designers, DFT engineers, test engineers, product engineers and foundry engineers that are, or will be, designing or characterizing the complex SoCs in 40-nm or 28-nm technology nodes.
Estimated length: 50 minutes, 10 minutes Q&A
Yervant Zorian, Chief Architect, Synopsys
Dr. Zorian is the Chief Architect at Synopsys for embedded test & repair products in Mountain View, California.
Formerly, he was Distinguished Member of Technical Staff AT&T Bell Laboratories, Vice President and Chief Scientist of Virage Logic and Chief Technologist at LogicVision. He received an MS degree in Computer Engineering from University of Southern California, a PhD in Electrical Engineering from McGill University, and an MBA from Wharton School of Business, University of Pennsylvania.
He is currently the President of IEEE Test Technology Technical Council (TTTC), the Vice General Chair of Design Automation Conference (DAC), the Editor-in-Chief Emeritus of Design & Test of Computers, the founder & chair of IEEE 1500 Standardization Working Group, and an Adjunct Professor at University of British Columbia.
Sandeep Kaushik, Product Marketing Manager, Synopsys
Sandeep Kaushik is the Product Marketing Manager for the Embedded Memory Test and Repair product line at Synopsys. Sandeep brings over 11 years of experience in the field of Design-for-Test. Sandeep holds a Bachelor's Degree in Electrical Engineering from the Indian Institute of Technology in Delhi, India and a Master's Degree in Electrical Engineering from Stanford University. He is currently working towards his Master's Degree in Business Administration from the HAAS School of Business, University of California, Berkeley.