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Reliability, Availability and Serviceability (RAS) for Memory Interfaces

Authored on: Jul 15, 2014 by Marc Greenberg

Technical Paper

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Smaller process geometries and higher DDR DRAM interface speeds are driving demand for new and more robust techniques for preventing, repairing and detecting memory errors. Some of these techniques are enabled by features in the latest DDR4 and DDR3 RDIMM standards, and others can be applied to any DRAM type. Collectively these techniques improve the Reliability, Availability, and Serviceability (RAS) of the computing system that adopts them. This white paper reviews some of the ways that errors can occur in the DDR DRAM memory subsystem and discusses current and future methods of improving RAS in the presence of these errors.
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