High Throughput GSPS Signal Processing Using Synthesizable IP Cores
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This white paper illustrates how parallel processing synthesizable IP cores available in Synphony Model Compiler enable Giga Samples Per Second (GSPS) throughput on FPGAs, and efficient area/power trade-offs for ASIC targets. In particular, we demonstrate how Parallel FFT, FIR, and CIC blocks enable users to scale throughput beyond achievable clock frequencies, and/or reduce power with sub-linear increases in area.
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