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Designing Low Power Sequential Circuits using Clock Gating

Authored on: Jan 23, 2014 by Bhanu Khera, Harsh Garg

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With shrinking technologies, rapid multiplication of clock frequencies and increasing emphasis on power reduction, low-power design is taking on a vital role. Design teams can no longer afford to just worry about isolation on big power domains. With most SoCs containing multiple sequential circuits, every little bit counts, thus, making it all the more important to design efficient low power designs. This paper describes an efficient way to design low power sequential circuits with effective clock gating. These sequential circuits are prominently used to design FSMs, clock dividers, counters etc in modern day designs.
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