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Tackling Verification Challenges with Interconnect Validation Tool

Authored on: Oct 1, 2013 by Dave Huang et al

Technical Paper

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As SoC capacity increases dramatically, verification complexity also grows, so the traditional ways of firing many direct tests, or applying a divide-and-conquer strategy, do not provide a holistic verification for SoC interconnects. A systematic approach must be adopted to tackle the challenge and make the process more efficient. In this paper, we discuss how Spreadtrum adopted Cadence Verification IP for AMBA Protocols and Cadence Interconnect Validator, an industry-leading tool for fabric verification. We convey how these tools helped us to improve verification efficiency, and we discuss a verification environment that we created with the Universal Verification Methodology (UVM).
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