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How to Achieve 10X Faster Power Integrity Analysis and Signoff

Authored on: Nov 7, 2013 by Jerry Zhao

Technical Paper

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In our mobile computing era, system-on-chip (SoC) design has become much more complex, with challenges from complex design rules on advanced process nodes, low-power circuitry design techniques, and increasing circuit sizes. Power integrity is a crucial part of successful design signoff. This paper discusses a new tool that speeds power integrity analysis and signoff by 10X compared to other technology available, while still providing SPICE-like accuracy. The tool integrates with a full suite of design implementation and signoff tools, together overcoming signoff challenges to deliver the industry's fastest design closure flow.
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