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An Innovative Simulation Workflow for Debugging High-Speed Digital Designs Using Jitter Separation

Authored on: Jun 7, 2013

Technical Paper

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This paper presents a new simulation workflow for jitter separation analysis. Jitter separation is a very promising tool that quickly identifies the sources of signal integrity degradation and thus enables easy optimization of a design to meet the low jitter requirements of multi-gigabit high speed digital SERDES devices.
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