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Novel CMOS Device Designs for Low Power Microelectronics

Authored on: Aug 23, 2013 by Leonard R. Rockett

Technical Paper

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The design and electrical characteristics of novel NMOS and PMOS composite devices that eliminate the momentary short circuit currents that flow during the logic transitions of CMOS logic gates are examined. These novel devices significantly reduce the switching noise and power dissipation in CMOS logic circuits without adversely impacting integration packing densities and with relatively minor impact on overall circuit speeds. CMOS logic gates designed with these novel devices have extended noise margins, the extended noise margins generally associated with Schmitt triggers, thereby enhancing the tolerance of the CMOS circuit to noise. This paper describes the novel device concepts and validates their effectiveness.
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Terry.Bollinger Posted Sep 3, 2013

This clever CMOS design strategy would seem well worth exploring for applications such a mobile devices where keeping the power drain low dominates over squeezing out the absolute maximum in speed. The speed penalty is not huge, the power and noise-reduction benefits are significant, and there does not appear to be any significant impact on overall CMOS densities.

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Toeff Posted Sep 6, 2013

I would guess that a reduction of the supply voltage VDD in conventional CMOS would lead to the same reduction in power dissipation with less impact on switching speed. Should at least by investigated with SPICE.

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Victor.Shadan Posted Sep 12, 2013

Nothing really new. Except these ideas have not been used, due to speed req. If the tech is faster than appl. then they could be used to reduce noise. About pwr, I go with lowering pwr supply idea and hope speed would not become any problem. Also I have seen many circuits that could be designed in a fashion that has less gates and smaller drivers needed. That by itself is a real art.

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samochi Posted Sep 13, 2013

I agree, simply lowering the power supply has the same effect as the novel circuit. I really don't see any advantages. Also, the speed penalty is enough in my mind to detract from this novel approach.

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Privatier Posted Jan 2, 2014

1. My experience with polydiodes is that the amount of lateral diffusion is not well controlled, thus the actual location of the diode in the polysilicon is not where the mask wants it to be. This lateral diffusion is in the order of several microns. As a result, the shorting silicide layer and contacts need to be placed far apart, not very appealing for submicron technologies. 2. Turn-on depends on the leakage of the diode, which is not well controlled. (Please show measured data from actual fabricated polydiodes, including matching characteristics.) As a consequence, the switching delay of a logic circuit is highly variable, and local variability will make designs almost impossible.

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