datasheets.com EBN.com EDN.com EETimes.com Embedded.com PlanetAnalog.com TechOnline.com  
Events
UBM Tech
UBM Tech
Welcome Guest Log In | Register

A Case for Nonuniform Fault Tolerance in Emerging Memories

Authored on: Jun 1, 2013 by Moinuddin Qureshi

Technical Paper

0 0
More InfoLess Info
As DRAM systems face scalability challenges, the architecture community has started investigating alternative technologies for main memory. These emerging memory technologies tend to suffer from the problem of limited write endurance. We propose to reduce the storage required for error correction by exploiting the observation that only a few lines require high levels of hard-error correction. Additionally, we propose Pay-As-You-Go (PAYG), an efficient hard-error resilient architecture that allocates error correction entries in proportion to the number of hard faults in the line.

Please disable any pop-up blockers for proper viewing of this paper.

0 comments
write a comment

Please Login

You will be redirected to the login page

×

Please Login

You will be redirected to the login page

×

Please Login

You will be redirected to the login page