Radiation Hardened CMOS Technologies using Buried Power Grids
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Radiation induced logic upsets and upset-causing phenomena (i.e., single-event upsets, single-event transients, single-event functional interrupts, prompt dose upsets, and prompt dose transients) are concerns for microelectronics used in aerospace and defense applications. Novel buried power grids that derive their power from a pre-existing feature of CMOS technologies ensure all charge funnels formed along the ion track following an ion strike are intercepted and partially neutralized, and they also significantly restrict the collection volume of excess charge following a high dose rate event; thereby enhancing radiation hardness. This paper describes the novel buried power grid design and the method for forming buried power grids in CMOS technologies for improved radiation hardness.