The demand for performance from portable computing devices, such as tablet computers and smartphones, has been steadily rising. One of the proposed solutions to increase battery life in such devices is to use CPUs with a different, power-efficient architecture. This paper introduces the "big.LITTLE" architecture launched by ARM, and its adoption for the Exynos line of processors by Samsung. The paper also discusses several key advantages of this architecture, compares it to other competing architectures, and demonstrates its efficiency and superiority over other architectures, especially in extending battery life in portable, handheld computing and communications devices.
In figure 7, the "Async Architecture" line was clearly meant to be below the "BLA" line in the B to C performance section. But some marketing guy had it changed.
This way the following argument makes sense:
"low-energy consuming applications prove
to be a much smaller drain on the device's power source (the battery),than occasional uses of
high-energy consuming applications"
I completely agree with you. Also I had once read an Intel research thesis where it was stating that "trying to execute an application/task on a slower clock for a longer possible duration consumes lesser power than executing a task at a higher clock and then shutting down the CPU core". the power consumption line of Async line is supposed to be below BLA line in the region B to C.
There is inconsistency on page 5-6. It states "If an L1 cache missoccurson one core,
the requested data are transferred from the L2 cache to the L1 cache via the SCU,asshown
bythe arrow„A‟ in Figure4. Becauseofthe differentclockdomainsfor the CPU,SCU,and L2cache,
additional clock cycles arerequired to complete this data transfer, resulting in a degradationof
the overall performance of the processor." This applies the BLA architecture too since L2 cache is at a different clock-power domain compared to the CPU-L1 cache.
Until and unless we see the statistical data on these architectures we cont just say the BLA is better compared to async architecture.
This is a marketing piece with many assumptions being made on the design. Fig7 has had some liberties applied to it as indicated above. "Asynchnronous" architectures can also demonstrate a similar curve to the BLA with efficient use of dynamic voltage and frequency scaling. By reducing both voltage and frequency there is dramatic reduction in both leakage and dynamic power.
The software/firmware overhead and complexity of managing this system with two different set of cores, knowing when to switch from one to the other and back are not trivial algorithms. Complexity such as this usually ends up not being used by the system designers.
Samsung Electronics is a provider of electronics components and products. The company consists of three main business units: Digital Media, Semiconductors and Information, and Communications Businesses.
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4 comments
write a commentaibarra Posted Feb 22, 2012
In figure 7, the "Async Architecture" line was clearly meant to be below the "BLA" line in the B to C performance section. But some marketing guy had it changed. This way the following argument makes sense: "low-energy consuming applications prove to be a much smaller drain on the device's power source (the battery),than occasional uses of high-energy consuming applications"
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DrHugo Posted Feb 29, 2012
I completely agree with you. Also I had once read an Intel research thesis where it was stating that "trying to execute an application/task on a slower clock for a longer possible duration consumes lesser power than executing a task at a higher clock and then shutting down the CPU core". the power consumption line of Async line is supposed to be below BLA line in the region B to C. There is inconsistency on page 5-6. It states "If an L1 cache missoccurson one core, the requested data are transferred from the L2 cache to the L1 cache via the SCU,asshown bythe arrow„A‟ in Figure4. Becauseofthe differentclockdomainsfor the CPU,SCU,and L2cache, additional clock cycles arerequired to complete this data transfer, resulting in a degradationof the overall performance of the processor." This applies the BLA architecture too since L2 cache is at a different clock-power domain compared to the CPU-L1 cache. Until and unless we see the statistical data on these architectures we cont just say the BLA is better compared to async architecture.
reply
Horaira Posted Feb 23, 2012
Please correct me if i am wrong , big.LITTLE architecture has just brought main processor and off loading processor in a single SoC.
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MikeSmith2011 Posted Mar 28, 2012
This is a marketing piece with many assumptions being made on the design. Fig7 has had some liberties applied to it as indicated above. "Asynchnronous" architectures can also demonstrate a similar curve to the BLA with efficient use of dynamic voltage and frequency scaling. By reducing both voltage and frequency there is dramatic reduction in both leakage and dynamic power. The software/firmware overhead and complexity of managing this system with two different set of cores, knowing when to switch from one to the other and back are not trivial algorithms. Complexity such as this usually ends up not being used by the system designers.
reply