RTL and gate-level Simulation is one of the oldest verification methods available in digital circuit design and maintains the status of the most popular and most reliable way of checking quality of your designs. This white paper uncovers key reasons why simulation is an important part of the design flow and shows most important features of modern simulators using Aldec Riviera-PRO.
Aldec is a supplier of VHDL and Verilog design-entry and verification software for programmable logic. It produces a suite of Windows-based EDA tools that allows implementation of designs using... Read More
Technical Paper
0
0
Download to Print
Add to bookmarks
0 comments
write a comment