Formal functional verification has gained popularity in the ASIC design and verification community because it can improve overall confidence and productivity. However, to optimize the value of this technology, it is important to select the most applicable areas or blocks within an ASIC or SoC. Recommendations put forth in the past simply have not kept pace with the latest innovations in formal technologies. As a result, this has significantly affected the applicability of formal functional verification.
This paper describes the innovations in formal technologies and methodology that benefit formal functional verification. It details how and why to apply this for the highest return.
Jasper Design Automation is a privately held electronic design automation (EDA) company delivering a formal functional verification solution capable of detecting all of the design bugs in most complex electronic design blocks.
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