Yield Optimization of Power-On Reset Cells and Functional Verification

Simulation-based yield optimization is becoming an important solution for increasing robustness of analog intellectual property (IP) blocks. This paper describes the yield optimization of a power-on reset cell as part of an analog IP library. Yield analysis of the initial design is performed and sensitivities with respect to process parameters are determined by Monte Carlo simulation.

The results of the yield analysis are used to determine a shift of the PMOS threshold implant dose, enabling a yield enhancement of the initial design. A re-design using simulation-based design centering is performed, resulting in a significant yield increase in consideration of the operating conditions.