Minimizing Interrupt Response Time
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This article will describe how a minimal yet guaranteed worst-case interrupt response time can be achieved in any type of electronic product, from simple control applications to the most complex, multi-process, I/O-intensive systems. We focus on minimizing response time for the highest priority interrupt (since lower priority interrupts may be delayed by it).
Reprinted in its entirety from ARM IQ Vol. 4, No. 1, 2005