This paper discusses a behavioral design methodology that allows designers to create hardware (ASIC, FPGA or SoC) from an arbitrary implementation independent C/C++ algorithm. We start by defining behavioral synthesis and then place it in the context of a behavioral design flow using industry case studies as examples. The goal of this paper is to give the reader an idea on the methodology benefits of behavioral design.
Forte Design Systems provides open, integrated tools for the hierarchical design and verification of large, complex electronics systems and ICs. It was formed from the merger of CynApps and Chronology.
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