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Power Noise Reliability Sign-off of Custom and Analog IPs

Posted on: Aug 20, 2013 | Duration: 25 min.
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Analysis technology addresses custom and analog IP including static and dynamic voltage drop, power and signal line EM and ESD integrity sign-off that are all critical. This Educast explains a full-chip SoC-level analysis flow to model noise coupling between high-speed digital and sensitive analog circuits through the silicon substrate, on-die metal power grid, or the shared package planes to optimize guard ring design.

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